The present invention relates to an apparatus for relieving the standby current fail of a memory device and, more particularly to an apparatus which completely relieves a memory device by suppressing the increasing standby current consumption when the standby current is failed by stress during or after fabricating process without any change of standby conditions in a memory device having NAND-type cell array structure, and by using the other data correcting way.
In the memory device having the NAND-type array cell, the word line voltage is above the threshold voltage of an enhancement cell for a selected cell (logic `H`), but below the threshold voltage of the enhancement cell for an unselected cell (logic `L`). In the standby mode of such a memory device, most of the word lines are in the logic `H` level, while the selected word lines by an input address applied to a chip are in logic `L` level. Thus, in the conventional memory devices having the NAND-type cell array which use polysilicon as the word lines, most of the cells are stressed by high voltage applied to the word lines during operation. This stress destroys the gate oxide of the transistors connected to the word lines, making the data reading of the cells impossible. These problems can be corrected by data correcting way such as redundancy and error correction code. But, because the voltage of the word lines holds high in the standby mode of the chip, the direct current path is formed through the destroyed parts of the cells, thereby causing the standby current fail.
FIG. 1 shows the circuit diagram of an embodiment of a conventional NAND cell array having N string selectors.
In FIG. 1, N string selectors ST1-STn are prepared, and to each string, bit lines B/L1-B/Ln and word lines W/L1-W/Ln are also prepared.
In normal data read mode, only one of the first and second string selectors SS1 and SS2 becomes the logic `H` level and one selected word line becomes the logic `L` level. In FIG. 1, m1 is an enhancement N-channel MOS transistor having a positive threshold voltage value, m2 is a depletion N-channel MOS transistor having a negative threshold voltage value, and m3-m6 having the enhancement or the depletion threshold voltage value according to programs.
For example, if the first string selecting signal SS1 and the second word line W/L2 were selected, according to address decoding, the voltage of the first string selecting signal SS1 is in the logic `H` level, and that of the second string selecting signal SS2 is in the logic `L` level. At this time, only the second word line W/L2 is in the logic `L` level, and the other word lines W/L1-W/Ln are all in the logic `H` level. Then, the transistors m1 and m2 are turned on, and the transistor m7 is turned off. As a result, the first bit line B/L1 is electrically connected to a node A, but disconnected with a node B by the transistor m7 being in cut-off state. Thus, the node B is floating. Also, the transistors m3, m5, m6 are always in turn-on state independent of program state, and the electrical connection of them to a ground node C' is determined according to the threshold voltage of the transistor m4 which uses the second word line W/L2 as the gate. If the transistor m4 is the depletion N-channel MOS transistor, it is turned on, even though the voltage of the second word line W/L2 is in the logic `L`. Thus, electrical path is formed between the first bit line B/L1 and the ground node C. By contrast, if m4 is the enhancement N-channel MOS transistor, it is turned off, forming no electrical path between the first bit line B/L1 and the ground node C'. The state of the cell selected by this decoding is read out by a sense amplifier connected to the first bit line B/L1 (not shown in FIG. 1).
In this circuit shown in FIG. 1, when the chip is in the standby mode, both the first and second string selecting signals SS1 and SS2 are in the logic `L` level and all the word lines W/L1-W/Ln are in the logic `L` level. Thus, if the gate insulator (silicon dioxide) of the transistor m4 is destroyed by the stress due to the high voltage applied to the word lines or the process defects, the current path is formed from the second word line W/L2 through the transistors m5 and m6. In this case, the transistor m4 can be relieved using the redundancy or the error correction code but in the standby mode, the current consumption of the chip is too large. Thus, the chip can not be relieved completely.